Signal distribution in an integrated circuit can be a challenging issue for integrated circuit designers. In the case when the signal to be distributed is a clock signal, conventional signal distribution typically utilizes a clock tree methodology to ensure that clock edges arrive at various locations throughout an integrated circuit such that set up and hold times are not violated. Clock trees typically utilize many stages of buffers and delay elements to ensure proper timing within the integrated circuit. Such buffers and delay elements not only delay the clock signals, but they also utilize a significant amount of power. The clock distribution circuitry may typically take as much as twenty percent of the overall power used by the integrated circuit.